1. Field of the Invention
The present invention relates to the design of electronic circuits, especially integrated circuits like VLSIs (Very Large Scale Integrated Circuits).
2. Description of the Related Art
Often electronic circuit designs are specified at the behavioral level and are then transformed to the register transfer level (RTL), to the gate level, to the transistor level and finally to the layout description. Before manufacturing an electronic circuit, the final design has to be validated completely. As part of this validation, the functional equivalence will be verified between two representations of said electronic circuit design, the original schematic and the final layout that resulted from the schematic.
A schematic is a logical description of an electronic circuit, its elements and their interconnections. Examples for circuit elements are resistors, logic gates, and complete  building blocks. A layout is a geometrical description of the physical implementation of an electronic circuit. Examples for such geometrical descriptions are shapes representing process masks used for the chip fabrication that represent actual physical layers, processing information or abstract placement information.
For example, “Hierarchical LVS Based on Hierarchy Rebuilding, Wongjong Kim and Hyunchul Shin, Proc. of the ASP-DAC 1998, page 379-page 384” and “Hcompare: A Hierarchical Netlist Comparison Program, Pradeep Batra and David Cooke, Proc. Of 29th ACM/IEEE Design Automation Conference 1992, page 299-page 304” describe hierarchical layout vs. schematic verification (LVS) approaches, wherein a purely functional comparison of two hierarchical netlists is performed. Especially, for LVS approaches graphical information about the physical circuit implementation is used to extract a functional netlist only.
Among the various data structures used for circuit design representations, sheets are a description of a part of a circuit design comprising references to other sheets, potentially graphical information about the electronic circuit like wires or on-chip metal shapes, and meta-data like placement information for circuit elements, parameters for referenced sheets, or information about connections between electronic circuit elements. Especially, sheets may contain layout or schematic data structures.
A circuit design representation can be comprised of various sheets that build up hierarchical tree data structures based on references to other sheets within the sheets. Typically, a major design component has a single top-level sheet only, also called the top-sheet. If a first sheet contains a reference to a second sheet, then the second sheet is also called a sub-sheet of the first sheet. A reference to a sheet is called an instance of the referenced sheet within the sheet comprising the reference.
The comparison of different versions of a particular version of a hierarchical design is very helpful during the circuit design development. It allows retracing design modifications and helps understanding their effects on the functionality and properties of the corresponding electronic circuit.
Usual approaches perform a manual comparison sheet by sheet ignoring the hierarchical relationships between the sheets of an electronic circuit design. Consequently, manually traversing all sheets in the hierarchy is a time-consuming and error-prone task. Therefore, a method for automatically detecting design changes within a design hierarchy is needed. The common solution to this problem is the so-called flattening of the sheet hierarchy: All referenced sheets are first incorporated into the top sheet, before carrying out the comparison. In this case, hierarchy information is lost and finding the specific sheet responsible for a design difference is tedious at best.